This invention relates generally to electronic design automation (EDA) of circuits and in particular to simplifying modes of an electronic circuit by reducing constraints of the modes.
Static timing analysis (STA) validates timing performance of a circuit design by checking various paths of an electronic circuit for timing violations. Performing static timing analysis for large electronic circuits can take significant time. Static timing analysis may be repeated multiple times during different stages of the circuit design. Furthermore, timing analysis is repeated multiple times for the same electronic design for various combinations of modes and corners.
Semiconductor device parameters can vary with conditions such as fabrication process, operating temperature, and power supply voltage. A circuit fabricated using these processes may run slower or faster than specified due to variations in operating conditions or may even fail to function. Therefore timing analysis is performed for various operating conditions to make sure that the circuit performs as specified under these conditions. Such operating conditions for a circuit are modeled using corners that comprise a set of libraries characterized for process, voltage, and temperature variations.
The timing analysis of a circuit is also repeated for different operating modes, for example, normal operating mode, test mode, scan mode, reset mode and so on. For example, a circuit used in a computer operates in a stand-by mode when the computer is in stand-by mode. Similarly, during testing phase, a circuit may be operated in a test mode. If each mode is verified for each corner condition, the total number of scenarios in which the design is verified is the product of the number of modes and number of corners. This results in the timing analysis being performed several times resulting in exorbitant costs.
One way to handle the large number of scenarios resulting from multiple modes and corners is to merge the modes into a smaller set, for example, a single mode. Since timing verification must be performed for the combination of modes and corners, reduction in the number of modes reduces the total combinations of modes and corners by a much larger number. For example, if there are 10 modes and 10 corners, the total number of combination of modes and corners is 10×10=100. However if the 10 modes are merged into one merged mode, the total number of combinations is reduced to 1×10=10. This is a 90% reduction in the number of combinations that need to be verified.
However, when multiple individual modes are merged into a single merged mode, the merged mode can be complex compared to each of the individual modes. For example, the number of clocks and exceptions in a merged mode is typically more than the number of clocks of found in any individual mode. Also, the number of timing constraints in the merged mode is typically more than the number of timing constraints of each individual mode. As a result, the analysis of the merged mode is slower than the analysis of individual modes and may require more resources with higher capacity for analysis. As a result, conventional techniques for merging modes result in high overall turn-around time for the electronic design process.